1. Field of the Invention
The present invention relates to data processing systems and, in particular, to a method for monitoring the sequence of instructions executed by a microprocessor without adversely effecting its operation.
2. Discussion of the Prior Art
A microprocessor is useful only if it is possible for designers of systems incorporating the microprocessor to "debug" their systems. The system designer must have the capability to observe the operation of the system under development, identify differences between the system's operation and its defined functional specification and then correct the system's design so that its behavior matches the functional specification.
One important aspect of observing the system's operation is following the sequence of instructions executed by the microprocessor. The system designer must be able to follow the sequence of executed instructions without slowing the system or causing the instruction sequence to differ from normal system operation.
Microprocessors are commonly designed so that transfer of control from one instruction to the next is determined both by the location and type of instruction executed and by whether an exception occurs. Exceptions are events, errors and special conditions, such as an attempt to execute an illegal instruction or an interrupt request signalled by a peripheral device, which are detected by the microprocessor.
Instructions executed by a microprocessor may be classified into three types: branch instructions, jump instructions and "other" instructions.
"Branch" instructions are those instructions that potentially transfer control to an instruction at a destination address calculated by adding a displacement value encoded into the currently executing instruction to the address of the currently executing instruction. Branch instructions can be "unconditional" or "conditional"; in the latter case, a test is made to determine whether a specified condition concerning the state of the microprocessor is true. A branch instruction is said to be "taken" either if it is unconditional or if it is conditional and the specified condition is true.
"Jump" instructions are those instructions that potentially transfer control to an instruction at a destination address calculated in a general manner that depends on the definition of the particular instruction. Examples of common jump instructions are "RETURN", which transfers control to an address that is read from the top of the stack in memory, and "CASE", which transfers control to an address that is located by using an operand's value to index into a table of addresses in memory. Like branch instructions, jump instructions can be "unconditional" or "conditional" and are said to be "taken" either if unconditional or if conditional and the specified condition is true.
The significant distinction between branch and jump instructions is that, for branch instructions, it is possible to calculate the destination address knowing only the instruction's encoding and location, whereas for jump instructions, the destination address generally depends on some data value that can vary, such as the contents of a register or memory location. For microprocessors that do not integrate a cache memory or a memory management unit "on-chip", the virtual addresses of all instruction and data references are available on the external interface of the microprocessor. Consequently, it is a straightforward matter to follow externally the sequence of instructions executed by the microprocessor.
For example, in the case of the National Semiconductor Corporation NS32032 microprocessor, after executing a taken branch or jump instruction, the next instruction is read from the destination address in memory using a special status code. The microprocessor also activates a program flow status interface signal whenever it begins executing a new instruction. It is, therefore, possible for the NS32032 microprocessor to monitor the sequence of executed instructions as follows:
1 For each taken branch or jump instruction, the destination address is available on the external interface;
2. Following the execution of a taken branch or jump instruction, the program flow status interface signal is observed to determine the sequence of instructions executed at consecutive memory addresses until the next taken branch or jump is executed; and
3. Data reads from memory locations that store the addresses of exception service procedures are detected on the external interface to determine when an exception has occurred.
However, for a microprocessor such as that of the present invention, which integrates a cache memory and a memory management unit on-chip, there are two problems that must be solved in order to externally monitor the sequence of executed instructions. First, since required instructions or data may be found in on-chip cache memory, not all memory references are observable on the microprocessor's external interface. This is because memory references that are located in the microprocessor's internal cache are performed without referring to external memory. Second, memory references observable on the microprocessor's external interface use physical addresses rather than virtual addresses. This is because the integrated memory management unit translates the virtual addresses generated by an executing program to the physical addresses used to access memory. In some circumstances, the translation will not be 1-to-1; that is, more than one virtual address can be translated to a single physical address. In such cases, it is impossible to determine the virtual addresses of memory references for an executing program by merely observing the physical addresses of the memory references on the external interface.